CMOS Compatible Photonic Processors

A photonics chip structure that enhances photodetector performance by integrating a waveguiding structure with a photodetector pad. The structure includes a photodetector with a semiconductor layer on a pad, and a waveguiding structure with a slot between two waveguide cores that adjoins the pad. The waveguide cores are segmented with portions extending into the slot, enabling efficient light coupling and improved responsivity while maintaining high bandwidth.

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Scalable photonic switch network for information processing, comprising a GMZI switch architecture that implements multiple permutation matrices through unitary mode interference, enabling flexible and scalable processing of multi-dimensional data.

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Method for selecting an optical path through a photonic circuit between an input port and an output port, comprising establishing at least one property of each constituent element and selecting the optical pathway based on the established property. The property can be optical loss, length, or other characteristics.

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A three-dimensional photonic chip architecture based on a VCSEL array, enabling the integration of deep neural networks (DNNs) directly onto the photonic chip. The architecture employs a single-mode VCSEL array with phase-locked operation, where the light is processed through the DNN layers. The DNNs are fabricated using 3D printing or microelectronic processes, with the VCSEL array serving as the photonic interface. This architecture enables the creation of high-density neural networks on photonic chips, overcoming traditional limitations of integrating neural networks with photonic architectures.

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Optical interconnect for high-speed, low-power, high-bandwidth chip-to-chip communication in multi-chip systems like AI processors. The interconnect uses optical fibers and on-chip photonics instead of electrical signals. It involves embedding an optical bridge chip with photodetectors and modulators between the electrical chips. The optical bridge reduces latency, power, and pin count compared to electrical interconnects. The optical bridge allows optical signals to be directly routed between chips without going through the edge of the chip. The optical bridge also addresses thermal issues by matching the temperature dependence of the bias voltage to the modulator's efficiency peak wavelength.

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A photonic tensor core (PTC) device for matrix multiplication that enables efficient processing of advanced AI tasks. The device employs slow-light Mach-Zehnder modulators for input operand encoding, hierarchical partial product accumulation, and multi-core architecture to maximize data sharing. The design eliminates the need for complex spectral encoding and wavelength division multiplexing, instead leveraging high-speed temporal encoding to achieve efficient matrix multiplication.

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A field-programmable photonic gate array (FPPGA) with improved spectral and time domain responses, comprising a photonic waveguide mesh arrangement with defective cells. The mesh arrangement includes hexagonal cells with variable side lengths and internal edges, as well as quadrangular cells with internal edges, to create a non-uniform waveguide structure. This structure enables flexible control over optical signal propagation and interference, enabling higher frequency operation and more complex circuit implementations compared to traditional uniform waveguide arrays.

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A photonic processor for matrix multiplication that employs segmented optical interferometers with phase shifters of varying dimensions. The processor represents matrix entries numerically through phase shifter modulation weights, enabling weighted combination of input values based on matrix entries. The processor controls phase shifters using digital inputs with binary states, where each state corresponds to a specific polarity and magnitude of phase shift. The processor performs matrix multiplication by controlling the phase shifters to generate an output that represents the product of the input vector and matrix.

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A photonic integrated circuit (PIC) that enables fully reconfigurable optical networks with sub-millisecond switching times and ultralow power consumption. The PIC employs a liquid crystal (LC) layer with a spatially varying refractive index that is selectively defined by an electrical field generated by a 2D electrode array. The LC layer is evanescently coupled to a waveguide layer, allowing light to be directed through the waveguide based on the spatially varying refractive index of the LC layer. The PIC can be used to implement large and dense optical network switches for applications in linear optical computing, quantum computing, neuromorphic computing, and AI accelerators.

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A photon computing method and array that enables high-speed, low-power, and highly integrated optical computing. The method employs a photon computing unit with an electro-optic modulator based on light absorption effect, which changes the absorption coefficient of the optical waveguide in response to electrical signals. The unit performs multiplication operations and is integrated into a crossbar switch matrix architecture to enable large-scale matrix multiplication operations. The array features a waveguide coupling device that enables efficient optical power transfer between units, and an optoelectronic conversion device that converts the optical output signal into an electric current signal. The system achieves fast modulation speeds, high integration density, and low energy consumption, making it suitable for high-performance computing applications.

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Differentiable optical processor comprising a plurality of optical layers, each comprising an optical filter with a transmission coefficient and a lens, where the filter scales input light and the lens performs a Fourier transform on the scaled light.

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A photonic die with reduced footprint for optical interconnects, comprising vertically stacked waveguides with tapered portions that eliminate the need for a transitioning section, enabling efficient optical signal transmission and processing in stacked photonic dies.

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A method for regulating an optical computing device that enables fine-tuning and re-calibration of neural network parameters. The method involves inputting an optical signal into a slab waveguide, detecting the output value, calculating the difference between the output value and a preset value, and regulating the crystal state of a phase change material in an adjustable diffraction groove to adjust the output value until it meets the preset value. The regulated device can then be used to implement multiple neural network calculations, achieving programmability and reconfigurability.

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Because the technical process is reaching its limits, the development of integrated circuits has entered the slow zone, which makes people gradually pay more attention to the new generation of integrated technologyphotonic integrated circuits (PIC). To give readers a general idea of PIC, this paper will first introduce the basic knowledge of photonic integrated circuits and compare photonic integrated circuits with traditional integrated circuits (IC) from different points of view, including their development history, properties, components, and potential. After that, some current technical innovations in optical communication, optical computing, and photonic quantum applications and development trends of photonic integrated circuits will be reviewed. Finally, three novel and promising technologies will be introduced to discuss how to solve the major challenge of improving integration. This work is not only a comprehensive and concise summary of the development of photonic integrated circuits so far but also an active exploration of solutions to the major challenges facing people in ... Read More

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Optical neural network architecture that improves beam-splitting accuracy in Mach-Zehnder interferometer (MZI) structures. The architecture includes two MZI paths with internal phase shifters and beam splitters, where the phase shifters are dynamically adjusted based on input and output optical signals to maintain a precise 50:50 beam-splitting ratio. This enables accurate optical linear operations, such as matrix-vector multiplication and convolution, in optical neural networks.

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A photon processor chip for accelerating photon computing and signal processing, featuring a processor and memory unit that utilize electromagnetic waves as a data carrier, with a processor arithmetic logic unit capable of executing two-bit arithmetic operations.

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AIM Photonics design enablement platforms supporting photonic integrated circuit design, interposer-based assembly, and design-for-test for a 300 mm CMOS-compatible silicon-photonics foundry are presented.

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A photonic integrated circuit (PIC) structure with a coupler for interlayer waveguide coupling, comprising a first waveguide core with a first end portion, a second waveguide core with a second end portion overlaying the first end portion, and a coupler between the first end portion and the second end portion. The coupler includes an additional waveguide core stacked vertically between and physically separated from the first end portion and the second end portion, facilitating low-loss optical signal transmission between the waveguides when the separation distance between adjacent overlapping end portions is too great.

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Optical multi-die interconnect bridging element (OMIB) for high-bandwidth, low-latency interconnects between semiconductor dies. The OMIB enables direct optical communication between dies, eliminating the need for electrical interconnects and their associated power consumption and signal latency. The OMIB comprises a photonic transceiver with modulator and photodetector components, integrated with electrical interconnects to connect to dies. This enables efficient, high-speed data transfer between dies, particularly beneficial for AI workloads that require rapid data exchange between processing and memory elements.

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An optical neural network that simulates a human brain's neural structure using linear optics and electronic feedback controls. The network comprises optical resonators and waveguides that mimic neurons and synapses, with electro-optical modulators providing nonlinear control and sensory input. The system enables rapid parallel signal transfer and can be scaled to achieve higher machine learning and artificial intelligence capabilities through wavelength multiplexing and feedback modulation.

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