CMOS Compatible Photonic Processors

A photonics chip structure that enhances photodetector performance by integrating a waveguiding structure with a photodetector pad. The structure includes a photodetector with a semiconductor layer on a pad, and a waveguiding structure with a slot between two waveguide cores that adjoins the pad. The waveguide cores are segmented with portions extending into the slot, enabling efficient light coupling and improved responsivity while maintaining high bandwidth.

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Scalable photonic switch network for information processing, comprising a GMZI switch architecture that implements multiple permutation matrices through unitary mode interference, enabling flexible and scalable processing of multi-dimensional data.

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Method for selecting an optical path through a photonic circuit between an input port and an output port, comprising establishing at least one property of each constituent element and selecting the optical pathway based on the established property. The property can be optical loss, length, or other characteristics.

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A three-dimensional photonic chip architecture based on a VCSEL array, enabling the integration of deep neural networks (DNNs) directly onto the photonic chip. The architecture employs a single-mode VCSEL array with phase-locked operation, where the light is processed through the DNN layers. The DNNs are fabricated using 3D printing or microelectronic processes, with the VCSEL array serving as the photonic interface. This architecture enables the creation of high-density neural networks on photonic chips, overcoming traditional limitations of integrating neural networks with photonic architectures.

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Optical interconnect for high-speed, low-power, high-bandwidth chip-to-chip communication in multi-chip systems like AI processors. The interconnect uses optical fibers and on-chip photonics instead of electrical signals. It involves embedding an optical bridge chip with photodetectors and modulators between the electrical chips. The optical bridge reduces latency, power, and pin count compared to electrical interconnects. The optical bridge allows optical signals to be directly routed between chips without going through the edge of the chip. The optical bridge also addresses thermal issues by matching the temperature dependence of the bias voltage to the modulator's efficiency peak wavelength.

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A photonic tensor core (PTC) device for matrix multiplication that enables efficient processing of advanced AI tasks. The device employs slow-light Mach-Zehnder modulators for input operand encoding, hierarchical partial product accumulation, and multi-core architecture to maximize data sharing. The design eliminates the need for complex spectral encoding and wavelength division multiplexing, instead leveraging high-speed temporal encoding to achieve efficient matrix multiplication.

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A field-programmable photonic gate array (FPPGA) with improved spectral and time domain responses, comprising a photonic waveguide mesh arrangement with defective cells. The mesh arrangement includes hexagonal cells with variable side lengths and internal edges, as well as quadrangular cells with internal edges, to create a non-uniform waveguide structure. This structure enables flexible control over optical signal propagation and interference, enabling higher frequency operation and more complex circuit implementations compared to traditional uniform waveguide arrays.

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A photonic processor for matrix multiplication that employs segmented optical interferometers with phase shifters of varying dimensions. The processor represents matrix entries numerically through phase shifter modulation weights, enabling weighted combination of input values based on matrix entries. The processor controls phase shifters using digital inputs with binary states, where each state corresponds to a specific polarity and magnitude of phase shift. The processor performs matrix multiplication by controlling the phase shifters to generate an output that represents the product of the input vector and matrix.

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A photonic integrated circuit (PIC) that enables fully reconfigurable optical networks with sub-millisecond switching times and ultralow power consumption. The PIC employs a liquid crystal (LC) layer with a spatially varying refractive index that is selectively defined by an electrical field generated by a 2D electrode array. The LC layer is evanescently coupled to a waveguide layer, allowing light to be directed through the waveguide based on the spatially varying refractive index of the LC layer. The PIC can be used to implement large and dense optical network switches for applications in linear optical computing, quantum computing, neuromorphic computing, and AI accelerators.

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A photon computing method and array that enables high-speed, low-power, and highly integrated optical computing. The method employs a photon computing unit with an electro-optic modulator based on light absorption effect, which changes the absorption coefficient of the optical waveguide in response to electrical signals. The unit performs multiplication operations and is integrated into a crossbar switch matrix architecture to enable large-scale matrix multiplication operations. The array features a waveguide coupling device that enables efficient optical power transfer between units, and an optoelectronic conversion device that converts the optical output signal into an electric current signal. The system achieves fast modulation speeds, high integration density, and low energy consumption, making it suitable for high-performance computing applications.

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Differentiable optical processor comprising a plurality of optical layers, each comprising an optical filter with a transmission coefficient and a lens, where the filter scales input light and the lens performs a Fourier transform on the scaled light.

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A photonic die with reduced footprint for optical interconnects, comprising vertically stacked waveguides with tapered portions that eliminate the need for a transitioning section, enabling efficient optical signal transmission and processing in stacked photonic dies.

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A method for regulating an optical computing device that enables fine-tuning and re-calibration of neural network parameters. The method involves inputting an optical signal into a slab waveguide, detecting the output value, calculating the difference between the output value and a preset value, and regulating the crystal state of a phase change material in an adjustable diffraction groove to adjust the output value until it meets the preset value. The regulated device can then be used to implement multiple neural network calculations, achieving programmability and reconfigurability.

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Because the technical process is reaching its limits, the development of integrated circuits has entered the slow zone, which makes people gradually pay more attention to the new generation of integrated technologyphotonic integrated circuits (PIC). To give readers a general idea of PIC, this paper will first introduce the basic knowledge of photonic integrated circuits and compare photonic integrated circuits with traditional integrated circuits (IC) from different points of view, including their development history, properties, components, and potential. After that, some current technical innovations in optical communication, optical computing, and photonic quantum applications and development trends of photonic integrated circuits will be reviewed. Finally, three novel and promising technologies will be introduced to discuss how to solve the major challenge of improving integration. This work is not only a comprehensive and concise summary of the development of photonic integrated circuits so far but also an active exploration of solutions to the major challenges facing people in ... Read More

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Optical neural network architecture that improves beam-splitting accuracy in Mach-Zehnder interferometer (MZI) structures. The architecture includes two MZI paths with internal phase shifters and beam splitters, where the phase shifters are dynamically adjusted based on input and output optical signals to maintain a precise 50:50 beam-splitting ratio. This enables accurate optical linear operations, such as matrix-vector multiplication and convolution, in optical neural networks.

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A photon processor chip for accelerating photon computing and signal processing, featuring a processor and memory unit that utilize electromagnetic waves as a data carrier, with a processor arithmetic logic unit capable of executing two-bit arithmetic operations.

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AIM Photonics design enablement platforms supporting photonic integrated circuit design, interposer-based assembly, and design-for-test for a 300 mm CMOS-compatible silicon-photonics foundry are presented.

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A photonic integrated circuit (PIC) structure with a coupler for interlayer waveguide coupling, comprising a first waveguide core with a first end portion, a second waveguide core with a second end portion overlaying the first end portion, and a coupler between the first end portion and the second end portion. The coupler includes an additional waveguide core stacked vertically between and physically separated from the first end portion and the second end portion, facilitating low-loss optical signal transmission between the waveguides when the separation distance between adjacent overlapping end portions is too great.

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Optical multi-die interconnect bridging element (OMIB) for high-bandwidth, low-latency interconnects between semiconductor dies. The OMIB enables direct optical communication between dies, eliminating the need for electrical interconnects and their associated power consumption and signal latency. The OMIB comprises a photonic transceiver with modulator and photodetector components, integrated with electrical interconnects to connect to dies. This enables efficient, high-speed data transfer between dies, particularly beneficial for AI workloads that require rapid data exchange between processing and memory elements.

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An optical neural network that simulates a human brain's neural structure using linear optics and electronic feedback controls. The network comprises optical resonators and waveguides that mimic neurons and synapses, with electro-optical modulators providing nonlinear control and sensory input. The system enables rapid parallel signal transfer and can be scaled to achieve higher machine learning and artificial intelligence capabilities through wavelength multiplexing and feedback modulation.

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A photonic integrated circuit (PIC) that integrates multiple photonic components, including waveguides, phase shifters, detectors, and switches, into a single die using semiconductor processing technology. The PIC enables high-density integration of photonic components, including quantum computing circuits, while maintaining low loss and high manufacturability. The PIC can be fabricated using a multi-wafer bonding process, where the waveguides are formed in an early stage to prevent high-temperature annealing from affecting other components. The PIC enables scalable quantum computing and quantum communication systems by integrating multiple photonic components into a single die.

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Integrated photonic circuit for processing quantum states of light in a generalized Mach-Zehnder interferometer (GMZI) configuration. The circuit has a first coupler to distribute the quantum state to multiple arms, and phase shifters on each arm to adjust the phases. A second coupler combines the phase-shifted light back together. This allows manipulating the quantum state by controlling the relative phases in the arms before recombining. The integrated circuit enables precise and efficient quantum state processing for applications like quantum computing and quantum communication.

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Coherent photonic circuits for computing applications, particularly neuromorphic computing, that enable scalable implementation of large-scale integrated analog or digital circuitry mimicking neurobiological function using optical computing. The circuits have coherent photonic neurons and neural networks that simultaneously compute multiple weighted sums over the same set of inputs for multiple sets of weights. The circuits split incoming light into multiple carrier signals, impart computational inputs onto the carriers, split each input signal further, impart weights onto each split signal, coherently combine the weighted signals, and measure the resulting optical outputs. This allows high-speed, energy-efficient optical implementation of linear algebraic computations like weighted sums over inputs.

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A photonic integrated circuit (PIC) structure with enhanced optical coupling between waveguides for robustness during transmission of high power optical signals. The structure includes a primary waveguide with a tapered end portion and at least one supplemental waveguide positioned laterally adjacent to and extending beyond the tapered end portion. The supplemental waveguide underlays/overlays the tapered end portion of the primary waveguide, enabling multiple mode matching locations between the primary waveguides and reducing light signal power density in any one path to prevent power-induced damage.

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A photonic integrated circuit (PIC) structure with robust high-power optical signal transmission. The structure includes a first waveguide with a tapered end portion and a second waveguide with a unique end portion featuring two branch waveguides positioned adjacent to the tapered end portion. The branch waveguides form a V or U shape and enable multiple signal paths between the waveguides, reducing power density and preventing damage from high-power optical signals.

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A photonic system with improved optical signal transmission efficiency, comprising a waveguide with a cavity adjacent to it for precisely aligning an optical fiber, and an isolation space formed under the waveguide to reduce signal loss. The cavity and isolation space are created simultaneously using a single masking element and etching process, allowing for efficient fabrication of the photonic system. The isolation space can be filled with air or interface with the waveguide's cladding layer, and can be vertically positioned below the waveguide's tapered end region. The system achieves high coupling efficiency between the waveguide and fiber, with a difference in TE and TM mode wave coupling efficiency of less than 10%.

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Modular optical phased array architecture comprising a multitude of photonic integrated circuit (PIC) tiles and electronic integrated circuit (EIC) tiles, where PIC tiles form an array of optical signal transmitters and/or receivers, and EIC tiles process electrical signals and communicate with PIC tiles. The architecture enables scalable and modular design, allowing for incremental expansion of the array size and aperture by adding more PIC and EIC tiles.

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A photonics chip structure that improves edge coupler performance through the incorporation of ring resonators. The structure includes an edge coupler with a longitudinal axis, a first ring resonator positioned at a first perpendicular distance from the axis, and a second ring resonator positioned at a second perpendicular distance from the axis. The ring resonators enhance mode conversion and confinement in the edge coupler, enabling more efficient light transfer between the chip and external light sources.

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A photonic processing system for matrix-vector multiplication that mitigates error sensitivity concentration by incorporating passive optical components at the center of the processor array. The system includes an optical encoder, a photonic processor with active and passive components, and an optical receiver. The photonic processor performs matrix-vector multiplication by propagating optical signals through a configurable array of active optical components, with passive components at the center to balance optical path numbers and reduce error sensitivity.

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Silicon photonics has established itself as a key integration platform, leveraging high-quality materials and large-scale manufacturing using mastered toolsets of complementary metal-oxide-semiconductor (CMOS) foundries. Chip-scale photonics offer unique promises for dense integration of versatile optical functions through compact and high-performance building blocks. Integrated photonics is now competing technology for many applications, spanning from telecom/datacom and interconnects up to quantum sciences and light detection and ranging (LIDAR) systems, among others. However, the lack of low-loss input/output chip interfaces can be prohibitive to successfully deploy multi-diverse device applications. Low coupling loss is essential in reducing overall power budget in photonic systems, impacting on-chip integration level. The light coupling from an off-chip environment into the planar waveguide platforms has always been a challenging research problem since the early years of integrated photonics. Optical interfaces formed on a photonic chip surface, rather than implemented on a chip... Read More

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A photonic bandgap phase modulator and optical filter bank that uses a photonic crystal structure to achieve high-speed modulation with low power consumption and reduced device size. The modulator operates by modulating the refractive index of the photonic crystal, enabling efficient phase modulation with minimal insertion loss. The device can be integrated into a photonic computing system and fabricated using various material platforms.

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A photonic tensor core processor that accelerates neural network inference by performing matrix multiplication using optical and electro-optical operations. The processor comprises modular sub-modules that perform multiply-accumulate operations through dot-product multiplications and coherent or incoherent summation. The photonic architecture enables parallel processing, low latency, and high energy efficiency, particularly for smaller matrix multiplications, while leveraging the inherent properties of light for enhanced computational throughput.

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An optical logic element for photoelectric digital logic operation and a logic operation method thereof, comprising a driver member and a photoelectric integrated member. The driver member drives the photoelectric integrated member to generate digital modulation information, loads the modulation information onto a coherent optical signal, and reads an electrical signal outputted by the photoelectric integrated member. The photoelectric integrated member performs digital logic operations on the coherent optical signal in a predetermined optical diffraction neural network, generates an electrical signal from the operation result, and outputs the operation result.

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A photonic computing system that performs vector operations using a photonic crossbar array with unit cells that include beam splitters and photodetectors. The system encodes input vectors in time-varying amplitudes or phases of optical signals, which are then transmitted through the crossbar array to perform matrix multiplication. The system achieves high-speed and low-power operation by leveraging the inherent parallelism of photonic processing and eliminating the need for digital-to-analog conversion.

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A Mach-Zehnder modulator for optical communication links that enables high-bandwidth transmission by incorporating optical delay elements and crossing elements between segments of the modulator. The modulator's architecture allows for precise control over the frequency response, enabling the creation of finite impulse response (FIR) filters that can compensate for signal distortion and bandwidth limitations in optical communication systems.

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A programmable photonic and quantum system that allows reconfigurable interconnection between classical and quantum signal processing blocks. The system uses programmable photonic analog units and reconfigurable interconnections on a photonic chip. It allows implementing quantum and classical circuits with optical feedback paths and linear multiport transformations by programming the resources and selecting input/output ports. The chip has classical and quantum building blocks connected to a reconfigurable optical core with tunable beam splitters. This provides basic optical analog signal operations like power/energy division and phase configuration. By programming the blocks and ports, it enables quantum circuits alongside classical circuits.

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Optical power splitter structure for photonics chips that improves tolerance to fabrication variations. The structure comprises three waveguide cores with arms positioned in a staggered configuration, where the central arm is laterally adjacent to the outer arms over different overlap distances. The larger overlap distance between the central arm and one outer arm provides an offset that compensates for dimensional inaccuracies, enabling consistent splitting ratios across different fabricated instances.

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Monolithic cointegration of electronics and photonics in the same silicon die is expected to enable a new realm of high-performance electro-optical systems for telecommunications, automotive, datacenter and sensing applications. As an alternative to integrating photonic devices into well-established microelectronic technologies, in this paper we report on the integration of CMOS electronic circuits in a commercial Silicon Photonics technology. Transistors with a threshold voltage of 1.84V, a gain factor of 4 A/V² and an Early voltage of 35V have been obtained by using the same masks as the photonic layer, without any additional technological steps in a truly zero-change paradigm. The paper reports a first application of this novel approach, showing time-multiplexed control of a 16-to-1 optical router enabled by an on-chip analog multiplexer.

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Abstract In recent years, with the further ministration of the semiconductor device in integrated circuits, power consumption and data transmission bandwidth have become insurmountable obstacles. As an integrated technology, photonic integrated circuits (PICs) have a promising potential in the postMoore era with more advantages in data processing, communication, and diversified sensing applications for their ultrahigh process speed and low power consumption. Silicon photonics is believed to be an encouraging solution to realize PICs because of the mature CMOS process. The past decades have witnessed a huge growth in silicon PICs. However, there is still a demand for the development of silicon PICs to enable powerful chipscale systems and new functionalities. In this paper, a review of the photonic components, functional blocks, and emerging applications for PICs is offered. The common photonic components are classified into several sections, including onchip light sources, fibertochip couplers, photonic resonators, waveguidebased sensors, onchip photodetectors, and modulators... Read More

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Abstract Programmable photonic circuits require an electronic control layer to configure and stabilize the optical functionality at runtime. Such control action is normally implemented by supervising the status of the circuit with integrated light monitors and by providing feedback signals to integrated actuators. This paper demonstrates that the control action can be effectively performed with electrical signals that are timemultiplexed directly on the photonic chip. To this aim, the necessary electronic functionalities are monolithically integrated in a conventional 220 nm silicon photonics platform with no changes to the standard fabrication process. By exploiting a nonconventional structure to implement metaloxidesemiconductor fieldeffect transistors, an electronic controller is codesigned into a programmable photonic circuit to enable a timemultiplexed readout of integrated photodetectors and sequential activation of thermal phase shifters with onchip electronic memory. The accuracy of the timemultiplexed control, achieved on a time scale of less than 10 ms, is demonst... Read More

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A photonic chip that enables simultaneous implementation of multiple photonics circuits with optical feedback paths and linear multiport transformations through a field-programmable architecture. The chip comprises equally-oriented programmable photonics processing blocks (PPABs) with parallel longitudinal axes, interconnected to form a waveguide mesh arrangement. The PPABs can be programmed to implement a wide range of functionalities, including optical feedback loops and linear transformations, through independent control of their coupling and phase-shifting configurations.

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A computing system comprising multiple integrated circuit packages (ICPs) connected by photonic channels, where each ICP includes an electronic integrated circuit (EIC) with processing elements connected by photonic channels into a hybrid electronic-photonic network-on-chip (NoC). The photonic channels enable high-speed, low-latency data transfer between processing elements, while the EIC performs compute-intensive tasks. The system achieves reduced power consumption and increased processing speed by maximizing data locality within each ICP and leveraging photonic channels for data movement.

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A photonics chip structure with improved edge coupler design that reduces power-dependent losses and prevents irreversible damage at high input optical powers. The structure features a waveguide core region with a lengthwise taper and a plurality of segments positioned between the core and the chip edge, with an overlapping waveguide core section positioned over the core region. This design enables efficient mode transformation and size variation while maintaining stable optical performance across a wide range of input powers.

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A photonic device for performing vector multiplications using Mach-Zehnder interferometers (MZIs) and optical attenuators. The MZI generates two output signals with controlled intensity difference, representing the multiplier, while the attenuators modulate the signals in proportion to the multiplicand. The device enables compact and reliable fabrication of large-scale optical matrix multiplication systems.

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Integrated optical circuit for optical neural networks that emulates the function of biological synapses. The circuit processes phase-encoded optical signals and provides phase-encoded output signals. It converts phase inputs into amplitude signals, weights them, and converts back to phase outputs. The circuit uses an interferometer, attenuator, and phase shifter to implement synapse functionality. This allows optical neural networks with compact, integrated, and power-efficient synapse circuits for applications like pattern recognition and classification.

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A photonics chip structure for an optical power splitter/combiner that reduces footprint and insertion loss. The structure comprises three waveguide cores with tapered sections that converge to form a power splitting/combing junction. The cores are positioned in different levels, with the central core's tapered section sandwiched between the tapered sections of the adjacent cores. This configuration enables efficient power transfer between the cores while minimizing the overall chip area.

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A photonics chip structure that enhances the robustness of silicon-based optical components, particularly optical modulators, against high input optical powers. The structure features a slotted waveguide component with two waveguide cores separated by a slot, and a third waveguide core positioned in a different level with an overlapping arrangement to the slot. This design enables improved power handling and reduced nonlinear effects, enabling the use of silicon-based optical components in high-power photonics applications.

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A photonic tensor processor for deep neural networks (DNNs) achieves ultralow latency and energy consumption through a weight-stationary architecture. The processor computes DNN layer outputs in a single shot using passive optical copying and static weighting of inputs, enabling scalable matrix-vector multiplication with latency of ~10 ns and energy consumption of ~10 fJ/MAC. This architecture overcomes the scalability limitations of existing photonic and electronic DNN accelerators, enabling the processing of large DNN models with significantly improved performance.

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A compact optical matrix multiplier for optical neural networks, comprising a 2x2 unitary matrix multiplier with a directional coupler or MMI coupler that integrates tunable phase shifters to perform linear transformations on optical signals. The coupler combines and splits input signals, while the phase shifters enable dynamic control of the optical path, enabling compact and programmable matrix multiplication for optical neural networks.

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Photonic computing system with high performance and efficiency for applications like AI that need large numbers of processors. The system uses an array of photonic processing units, each with an array of photonic guiding units, to perform optical computing tasks. The photonic processing units are connected by optical connectors that couple light fields between adjacent units. This allows communicating processing units to form a network for distributed optical computing.

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