AI Based Electronic Design Automation

An information processing system for designing semiconductor devices, comprising a first component that receives code and configuration data, a second component that realizes the semiconductor device based on the code and configuration data, and a third component that processes design history documents generated by the second component using a large-scale language model to provide proposals for modifying the code and configuration data.

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Training a machine learning system for automated design by using a dataset of high-level specifications and their corresponding design representations to enable early-stage optimization and size estimation. The trained system can then be used to determine a design representation for a given high-level specification, enabling efficient automated design processes.

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Automated design of safety-critical systems using High-Level Synthesis (HLS) with integrated safety features. The method modifies the initial high-level specification to incorporate safety constraints and functionality, enabling early consideration of safety requirements in the design process.

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Lately, architects have begun to favour a more result-oriented way of working based on artificial intelligence (AI) and its use for automation and software applications operation that support work with design data. The research aims to identify and systematise data on computer tools using artificial intelligence algorithms and the prospects for its development in architectural activities. The use of AI algorithms in architectural design is characteristic of all its stages, from the conceptual phase and basic design levels to detailing, development of design documentation, and future implementation, which is why various computer tools are available. The scientific paper describes three groups of AI software products. The first group includes software for architectural activities with AI-based functionality. The second group involves additional plug-ins with AI algorithms, i.e., independently compiled software modules installed and connected to the main programme, expanding its capabilities. The third group comprises online AI platforms, many of which are already available on the Inter... Read More

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A system for designing and testing electronic devices using artificial intelligence, comprising a first AI model that generates verification code from a product design, a second AI model that adjusts the design based on the verification code, and a verification engine that executes the verification code to generate a verifiability score. The system iteratively refines the design until the verifiability score meets a threshold, enabling automated verification and design optimization.

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This study explores the synergistic potential of integrating artificial intelligence (AI) with design thinking, aiming to enhance innovation and problem-solving capabilities in various domains. Beginning with a comprehensive examination of design thinking principles and methodologies, the research provides a foundational understanding of its core concepts. Subsequently, it investigates the capabilities of AI that can complement and augment the design thinking process. This includes an analysis of existing AI applications across different fields, highlighting their effectiveness and potential contributions to creative and strategic design processes. Central to the study is the integration of AI principles and tools within the framework of design thinking. Through a detailed review of AI techniques, the research identifies specific applications where AI can enhance ideation, prototyping, and user-centered design phases. Furthermore, it maps out how AI-driven solutions can be seamlessly incorporated into each stage of the design thinking process. This integration aims to optimize creati... Read More

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A system and method for predicting static voltage drop (SIR) violations in a clock tree synthesis (CTS) layout before routing, using machine learning models trained on CTS layouts with known SIR violations. The system receives CTS layout data, inspects each region, and compares it to the trained models to predict potential SIR violations. If no violations are predicted, the layout can be routed directly, avoiding the need for post-routing SIR analysis.

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Over the past fifty years, Electronic Design Automation (EDA) tools have played a crucial role in the semiconductor industry, assisting in the design, simulation, and manufacturing of integrated circuits (ICs). However, the sophisticated nature of these tools often demands extensive expertise, which can be a barrier for many users. Mastery of these tools necessitates specialized knowledge and skills, including comprehension of complex algorithms, design methodologies, and tool-specific workflows. To address this challenge, this paper introduces a machine learning (ML) based information retrieval system designed to enhance the usability of EDA tools. The objective of this system is to simplify user interactions and make EDA tools more accessible to designers, regardless of their expertise level. The main idea of this ML-driven system is to provide a chatbot-like interface that facilitates efficient, context-aware searches and offers interactive, step-by-step guidance on using various tool functionalities. By integrating natural language processing and machine learning techniques, the ... Read More

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Method for improving timing analysis to silicon correlation using machine learning to model physical parameter shifts between golden and existing models, generating a calibration database to calibrate static timing analysis (STA) behavior based on silicon data, and using the calibrated STA to generate updated timing data.

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Method for testing integrated circuit designs using machine learning techniques to select critical test cases. The method receives a plurality of test cases, generates an embedding data set, and clusters the test cases based on their characteristics. Critical test cases are selected from the clusters, and the integrated circuit is timed based on these critical test cases. The method can also use timing analysis data to select critical test cases.

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A neural network modeling method for semiconductor design that improves model consistency through active sampling and selective retraining. The method trains a regression model using simulation data, checks its consistency, and selectively collects additional data from regions where predictions fail. This targeted data collection enables efficient retraining of the model, improving its accuracy and reducing the need for manual intervention.

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A computer-aided design system for electronic circuits that uses artificial intelligence to automate the selection of components based on design specifications and performance requirements. The system receives a design specification, determines a set of performance ranges, and generates multiple solution variants by querying a database of components and applying AI algorithms to select components that meet the performance requirements. The system presents the solution variants in a graphical user interface, allowing users to visualize and compare the performance of different design options.

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A computer-aided design (CAD) system that incorporates an artificial intelligence advisor to inform users of potential hardware limitations and constraints during the design process. The AI advisor analyzes the design and identifies potential issues based on a knowledge graph constructed from project archives, expert knowledge, and industry standards. It generates recommendations to prevent hardware damage and ensures safe operation, providing real-time feedback to the user through the CAD interface.

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Model-Driven Engineering (MDE) provides a huge body of knowledge of automation for many different engineering tasks, especially those involving transitioning from design to implementation. With the huge progress made on Artificial Intelligence (AI) techniques, questions arise for the future of MDE such as how existing MDE techniques and technologies can be improved or how other activities which currently lack dedicated support can also be automated. However, at the same time, it has to be revisited where and how models should be used to keep the engineers in the loop for creating, operating, and maintaining complex systems. To trigger dedicated research on these open points, we discuss the history of automation in MDE and present perspectives on how automation in MDE can be further improved and which obstacles have to be overcome in the medium and long term perspective.

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Automated design of physical systems using generative models. The system trains a generative model to output initial system topologies based on functional and behavior requirements. The model is trained on a large dataset of system diagrams, such as process flow diagrams, from which topology information is extracted and converted into a formal language representation. The trained model generates a topology for a to-be-designed system, which is then instantiated with components and their parameters through optimization techniques.

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In the context of digitalization, the continuous progress of science and technology and the increase in the degree of informationization, the traditional digital design means are more and more unable to meet the needs of today's diversified design, so the addition of artificial intelligence technology has also become an irreversible trend in the design means. As a powerful tool and technical means, artificial intelligence can largely improve the quality and efficiency of design, and can form a knowledge base and experience base through the accumulation of a large amount of data to provide reference and guidance for subsequent design work. Through the practice of AI in the field of design in recent years, the article combs and summarizes its excellent examples, focuses on the pioneering and mining of AI-driven design innovation, and thus leads to the discussion of the future development of intelligent design.

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Rapid advances in artificial intelligence (AI) and machine learning have had a significant impact on various fields, including electronic design automation (EDA). This study aims to compare current EDA routing algorithms with AI-based routing algorithms, highlighting their respective advantages and limitations. Through a comprehensive analysis of existing EDA routing algorithms and artificial intelligence-based technologies, this study explores the applicability of these algorithms in different EDA scenarios, with a focus on their effectiveness and efficiency in routing tasks, and aims to compare and contrast traditional and AI-based routing algorithms in the context of electronic design automation. It also shows that the current AI technology will play an important role in the future development of EDA software. Therefore, the combination of AI technology may be the focus of EDA software development, so as to help elucidate the evolving landscape of EDA and provide insights into the potential future direction, and provide a a comprehensive understanding of their underlying methodolo... Read More

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A method for automatic routing of electronic circuits that decouples routing grids from core algorithms, enabling efficient handling of complex design rule checking (DRC) rules from various foundries. The method generates a routing graph based on DRC rules and dynamically updates it in real-time as the user creates routing segments and vias, allowing for fast and accurate routing of complex digital and mixed-signal designs.

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A method for predicting circuit design performance and identifying optimization opportunities using machine learning models. The method determines a set of circuit design features, applies a predictive model to estimate performance metrics, and an explanation model to quantify feature contributions. It then selects the most impactful feature and retrieves a corresponding optimization recipe from a database, enabling targeted design improvements.

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A method for generating a semiconductor device layout with improved accuracy and reduced computation, comprising: receiving a first layout; performing machine learning-based process proximity correction (PPC) to generate a second layout; and performing optical proximity correction (OPC) on the second layout to generate a third layout.

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The use of artificial intelligence (AI) technology in computers has increased recently, as evidenced by the numerous research electronics goods. Many of these researchers have specialists who link and mix artificial intelligence (AI) in computers with electronic design. As a result, it makes it possible for a lot of researchers to continue researching the more advanced growth path of computer AI technology. It explores the features and value of computer AI technology in the design of electronic products in more detail and suggests that applying computer AI to the creation of electronic products is challenging. Additionally, this essay highlights the pertinent techniques and approaches for using AI in the creation of electronic products. Additionally, this can broaden the applications of computer AI technology, which is now the cornerstone of study into the design of electronic products.

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A system and method for generating manufacturable integrated circuit layouts using machine learning. The system trains artificial neural networks on labeled datasets of compliant layouts, then deploys the trained models to identify design rule violations and generate transformations to create compliant layouts that preserve circuit functionality.

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A method and system for instrumenting electronic designs to identify useful untested states, particularly for analog and mixed-signal integrated circuits. The system captures metadata from the netlist to enable efficient generation of valid states based on design specifications, manufacturing variations, and functional variations. This allows for automated assessment of verification completeness and identification of untested states, reducing the need for manual verification and improving design efficiency.

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An assistance system for designing industrial automation systems that adheres to engineering constraints, comprising an assistant component for building formal specifications of constraints and a machine learning-based advisor component that iteratively trains a policy network to recommend engineering actions to resolve constraint violations. The system integrates with existing engineering tools and leverages domain models and engineering actions to provide meaningful recommendations.

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A system for automating analog circuit design using machine learning. The system analyzes electronic design schematics to identify required and optional circuit features, then uses machine learning models to predict optimal device placement and sizing constraints. The system can also generate sizing constraints for analog circuits based on machine learning predictions, eliminating the need for manual constraint creation.

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This keynote paper highlights the interaction between emerging technologies and software tools to enable the current evolution of electronic design automation systems.

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Abstract Engineering design has proven to be a rich context for applying artificial intelligence (AI) methods, but a categorization of such methods applied in AI-based design research works seems to be lacking. This paper presents a focused literature review of AI-based methods mapped to the different stages of the engineering design process and describes how these methods assist the design process. We surveyed 108 AI-based engineering design papers from peer-reviewed journals and conference proceedings and mapped their contribution to five stages of the engineering design process. We categorized seven AI-based methods in our dataset. Our literature study indicated that most AI-based design research works are targeted at the conceptual and preliminary design stages. Given the open-ended, ambiguous nature of these early stages, these results are unexpected. We conjecture that this is likely a result of several factors, including the iterative nature of design tasks in these stages, the availability of open design data repositories, and the inclination to use AI for processing computat... Read More

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In the rapidly growing field of electronic design automation (EDA), professional software such as KiCad, Cadence , and Altium Designer provide increasingly extensive design functionalities. However, the intricate command structure and high learning curve create a barrier, particularly for novice printed circuit board (PCB) designers. This results in difficulties in selecting appropriate functions or plugins for varying design purposes, compounded by the lack of intuitive learning methods beyond traditional documentation, videos, and online forums. To address this challenge, an artificial intelligence (AI) interaction assist plugin for EDA software named SmartonAl is developed here, also KiCad is taken as the first example. SmartonAI is inspired by the HuggingGPT framework and employs large language models, such as GPT and BERT, to facilitate task planning and execution. On receiving a designer request, SmartonAI conducts a task breakdown and efficiently executes relevant subtasks, such as analysis of help documentation paragraphs and execution of different plugins, along with leverag... Read More

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Timing and placement co-optimization for engineering change orders (ECOs) in integrated circuit design. The system integrates timing analysis and placement optimization to evaluate cell movements based on timing slack, preventing timing degradation while creating space for ECO cells. It determines acceptable placements for ECO cells and acceptable movements of current cells to create space, limiting cell movements based on calculated timing slacks to prevent additional timing violations.

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A method for improving the performance of static timing analysis (STA) reporting in electronic design automation (EDA) tools. The method employs a parallel command infrastructure (PCI) to enable multithreading of reporting commands, particularly the report timing (RT) command, which is a dominant contributor to STA runtime. The PCI identifies and groups RT commands based on dependencies, allowing them to be executed concurrently in parallel threads, thereby optimizing overall STA performance.

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Method for electronic design closure with reduced memory requirements, comprising determining a timing graph and compact timing data for a dominant analysis view of a set of analysis views, identifying a reduced set of dominant views through timing dominance analysis, loading timing data for the reduced set, and performing design closure using the loaded data and reduced views.

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A system for predicting timing path frequencies in integrated circuit designs using statistical analysis. The system trains a model on timing path properties and operating conditions from a set of sample paths, then uses static timing analysis to determine an operating condition for a specific path. The trained model is then used to predict additional operating conditions for the path, enabling faster and more comprehensive timing analysis across multiple operating conditions.

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A method for identifying and correcting systematic defects in integrated circuits (ICs) by grouping paths in the IC layout diagram based on dominant features and testing each group. When a path fails, the dominant feature is identified as the root cause and corrected in the IC layout, library, or manufacturing process, enabling simultaneous fixes for multiple paths sharing the same dominant feature.

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A system and method for reducing the design space size in electrical circuit design using machine learning. The system predicts a subset of feasible circuit designs from a component library using a machine learning model, and then generates a final design solution based on the predicted designs and specified design criteria.

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Automated generation of electronic circuit schematics and layouts using parameterized sub-circuit components. The system receives circuit specification parameters, selects predefined sub-circuit schematics based on the parameters, determines connections between the sub-circuits, and generates a layout script. The system then converts the circuit specification into a circuit schematic and layout by selecting and connecting the sub-circuit schematics, converting the schematic into layout instances, and positioning the instances according to the layout script.

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A computer-aided design (CAD) system that provides intelligent assistants to enhance design productivity and reduce design redundancy. The system includes a search assistant to locate existing designs, a templating assistant to generate new designs based on templates, a segmentation assistant to identify design variations, a design synthesis assistant to combine existing designs, and an auto-complete assistant to automate repetitive design tasks. These assistants leverage graph representations and machine learning models to provide efficient design solutions and reduce the burden of maintaining large design libraries.

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A computer-implemented method for determining a printed circuit board layout and/or information for placing groups of components on a printed circuit board. The method includes receiving data of a circuit diagram of the printed circuit or identification data of a circuit diagram of the printed circuit stored in a first database and retrieving the layout of the printed circuit associated with the identification data in the first database. The method further comprises extracting first component group and/or layout data from the circuit diagram data of the printed circuit board layout.

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A neural network-based compact modeling methodology for advanced FET modeling that enables fast and accurate simulation of semiconductor devices. The methodology employs a novel loss function that omits charge values during training, allowing direct use of capacitance-voltage data. It also introduces an initial weights setting option using pre-trained models, local fitting for multiple device instances, and a smoothing technique for voltage inputs. The methodology achieves high model accuracy, fast training times, and efficient SPICE simulation times, making it suitable for Design-Technology-Co-Optimization (DTCO) activities.

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A machine learning-based IC design flow that predicts timing and other design labels in later stages of the design process, enabling earlier optimization and improved quality of results. The approach extracts features from the design at an earlier stage and trains a model to predict the expected design labels at a later stage, allowing for targeted optimization and reduced design iterations.

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A neural network-based approach to electronic design automation (EDA) for generating computer chip floorplans. The system employs a reinforcement learning-trained neural network to optimize chip placement, leveraging a reward function that measures floorplan quality based on characteristics such as power consumption, heat generation, and timing performance. The approach enables rapid generation of high-quality floorplans, eliminating the need for weeks-long manual processes and human expert involvement.

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A method for optimizing on-device neural networks using a Sub-kernel Searching Module (SSM). The method trains a Big Neural Network Model (B-NN Model) to generate inference results, then uses the SSM to identify constraints and generate architecture information for a specific sub-kernel suitable for the input data. The B-NN Model is optimized using the sub-kernel architecture to generate a Small Neural Network Model (S-NN Model), which is trained on the input data. The SSM is trained using the losses between the B-NN Model and S-NN Model inference results.

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A method of predicting electronic design performance using machine learning, comprising training a machine learning model to predict performance based on input design parameters, and iteratively refining the model through EDA tool evaluations and parameter updates until desired performance is achieved.

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Weight matrix circuit for improving calculation accuracy of an artificial neural network circuit using resistive memories. The circuit includes n input lines, m output lines, and nm resistive memory devices each connected to the n input lines and the m output lines and each having a non-linear current-voltage characteristic.

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Current industrial practice does not reflect the opportunities provided by state-of-the-art design automation methods. The limited application of computational methods to support the design process by automating design tasks is caused by the lack of methods for comprehensive design automation task definition. Therefore, potential design automation tasks are not recognized and already deployed solutions lack integration to design practice from a product lifecycle management (PLM) perspective. In response to these shortcomings, this work proposes a method for identification and integration of design automation tasks that features collaborative workshops and enterprise architecture modelling for comprehensive analysis of design processes including its technological environments. The method applies design automation task templates that contextualize the knowledge levels required for design automation task definition and the design process including its technological environments. Evaluation with three industrial cases shows that the method enables efficient identification and integration... Read More

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Maintaining high product quality while reducing cost is essential for mass-customised products, requiring continuous improvement of the product development process. To this end, design automation should be utilised in all stages of a products develop process and lay the foundation for automation of repetitive tasks throughout the process from interaction with the customer to design and production in order to mitigate errors and minimise costs. In this paper, a design automation and production preparation framework is proposed that can facilitate automation from initial stages via CAD to production. Examples of the framework are shown in the shape of proof-of-concepts systems developed by master students in the context of a course in design automation at Linkping University. Included disciplines such as automated planning of robot assembly paths, CNC manufacturing files and production drawings are described, based on design automation, Knowledge-Based Engineering, and design optimisation. Additionally, variations of the framework are implemented at three SMEs, and the results thereo... Read More

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Automatically generating sizing constraints for analog and mixed-signal electronic designs using machine learning models that analyze the design schematic and layout to learn device size parameters, parameter ranges, and matching relationships.

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Machine learning-based design of self-adapting microelectronic circuits that can automatically optimize performance characteristics across a wide range of conditions. The design employs an AI model that learns circuit behavior from simulation data and generates adaptive control signals to compensate for manufacturing variations, environmental factors, and process defects. The model is trained using a comprehensive dataset of circuit performance metrics under various operating conditions, enabling the creation of self-adapting circuits that can maintain precise specifications even in challenging environments.

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System for determining timing path frequency in integrated circuit design, comprising a design management component that generates a trained model representing timing path properties and operating conditions based on sample timing paths with characteristics determined by random seed values, and a static timing analysis component that performs timing analysis on the design and uses the trained model to predict additional operating conditions.

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A method for integrated circuit (IC) design with delay verification that uses machine learning (ML) models to predict signal slew rates, net delays, and cell delays. The method extracts feature values from a user design and uses these values to load and operate ML models for slew rate, net delay, and cell delay prediction. The predicted values are then sent to design flow tools, which iterate the user design until timing violations are resolved.

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A method for predicting the frequency and power distribution of manufactured integrated circuits (ICs) based on design stage analysis. The method involves creating a library of IC cell types and their corresponding behavioral values for various process variations, correlating the IC design with the library, and predicting the frequency and power distribution of manufactured ICs. The library is updated using post-manufacturing data to improve future analysis and prediction processes.

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