Dynamic Voltage and Frequency Scaling for Power Efficiency

Selectively throttling subsystems of a battery-powered computing device to prevent brownouts and improve user experience by avoiding excessive battery voltage droops. When ROP subsystem power usage is high, those devices are throttled before processor cores. Multiple layers of brown-out prevention are applied asynchronously to different domains and subsystems. The throttling is triggered when total power consumption exceeds thresholds, with ROP subsystems throttled first. This prevents aggressive throttling of the processor cores.

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A method for dynamically optimizing processor frequency and voltage to maximize performance while maintaining reliability. The method involves analyzing processor states and conditions to determine optimal frequency scaling indexes, which are then used to select a target clock frequency. The method also includes adaptive voltage control to mitigate voltage droops, with droop mitigation enabled when the core voltage falls below a threshold. The voltage control loop offsets load line uplift to maintain voltage below the reliability limit, while protecting against performance loss from excessive droop mitigation.

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A power management system for processing units that dynamically adjusts current draw in response to sudden workload changes, preventing performance degradation and maintaining functionality during rapid transitions between low and high processing demands.

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A Dynamic Voltage and Frequency Scaling (DVFS) controller that optimizes performance and power efficiency by dynamically adjusting operating voltage and frequency based on resonance frequency calculated from the entire power system's frequency response, including the power management unit, power delivery network, and processing subblocks. The controller receives feedback signals from the system and updates voltage and frequency control signals to maintain stable operation even in voltage drooping conditions.

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A method for adjusting CPU frequency in mobile devices that improves energy efficiency by dynamically adjusting the target CPU load based on the actual load and a threshold error. The method includes setting the CPU frequency for a current cycle based on the prior cycle's load and target load, detecting the current load, and adjusting the frequency based on the difference between the target and actual loads. The target load is dynamically adjusted based on the load error and a threshold error, enabling the CPU to operate at the optimal frequency for the current workload.

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A dynamic voltage and frequency scaling (DVFS) system for multi-core processors that dynamically allocates power to individual cores based on their performance and power consumption. The system receives power and performance metrics from each core, calculates a power margin based on a target power budget, and adjusts the power index of each core accordingly. The system also determines whether each core can increase its bus frequency or core frequency based on utilization and bandwidth metrics, and adjusts these frequencies accordingly.

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Dynamic voltage and frequency scaling (DVFS) technique for integrated circuits with multiple processing cores sharing a voltage rail. The technique uses a ruler-follower mechanism where a core can register as a ruler or follower, with the ruler core influencing the frequency of follower cores. The DVFS manager adjusts core frequencies and voltage rail based on mapping rules and constraints to optimize high voltage residency and minimize power consumption.

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Apparatus for dynamic voltage and frequency scaling (DVFS) of integrated components in a System on a Chip (SoC), comprising a plurality of components with assigned throttling priorities and a logic to selectively throttle components based on their priority order.

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Adaptive voltage scaling system for computing systems that optimizes power consumption by dynamically adjusting operating voltage in real-time based on workload demands, while maintaining stability and reliability through continuous monitoring of physical parameters and operating conditions. The system integrates dynamic voltage and frequency scaling (DVFS) with adaptive voltage and code scaling (DVCS) to achieve optimal energy efficiency and performance.

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A power management system for extension cards or circuit boards that actively regulates current consumption in real-time. The system includes a current sensing circuit that measures the current drawn by the extension card from the motherboard, and a controller that generates a control signal based on the measured current compared to a target current. The control signal is applied to the extension card to adjust its current consumption, enabling dynamic power management that can respond to changing system conditions.

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Power management in integrated circuits like system-on-chips (SoCs) to reduce power consumption. The power management unit (PMU) monitors power supply voltages, currents, and temperatures in the SoC and triggers power reduction if conditions exceed thresholds. The PMU has wired and serial trigger circuits to communicate with the SoC. Wired circuits provide fast responses for voltage and current conditions, while serial circuits provide slower responses for temperature. The PMU triggers power reduction to prevent erroneous operation if supply voltages drop, currents exceed limits, or temperatures rise.

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A system and method for power throttling in multicore systems that measures current draw on the main power rail to detect power surges and trigger throttling when thresholds are exceeded, including both absolute current levels and current slew rates.

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A voltage regulator (VR) control method that predicts large load current transients and proactively increases its response speed to minimize voltage undershoot/overshoot. The method uses predictive load transient information from the load device to generate a turbo signal that activates the VR's high-response mode before the transient occurs. The VR can also generate a power throttling signal to reduce load current transients when operating in high-response mode.

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Efficient power management for integrated circuits, particularly in multi-core processors, is achieved by dividing functional blocks into separate power domains, each with its own voltage regulator, allowing for independent power management and reduced power consumption.

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A semiconductor device that controls temperature through dynamic voltage frequency scaling (DVFS) by monitoring the operating clock's critical path and adjusting the supply voltage in response to frequency comparison results. The device includes a thermal management unit, clock management unit, power management unit, and DVFS block with a critical path monitor, frequency monitor, target frequency module, adder, and decide voltage module. The DVFS block compares the target frequency with the current frequency and generates deciding results to control the supply voltage, which is then provided to the clock generator.

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A method and apparatus for detecting voltage droop in a processor's supply voltage. The method involves receiving a clock signal at a tap sampled delay line powered by the same supply voltage, splitting the signal into two paths, sampling the signal at multiple taps, and measuring the change in clock edge position between samples to determine the magnitude of voltage droop. When voltage droop is detected, the method generates a lower-frequency clock signal to mitigate the droop. The apparatus includes a tap sampled delay line and clock signal modification circuitry to implement this method.

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A computational digital low dropout (CDLDO) regulator that computes a required solution for regulating an output supply as opposed to traditional feedback controllers. The CDLDO regulator autonomously tunes out the effects of process-voltage-temperature (PVT) and other non-idealities, enabling GHz-speed regulation and making fast dynamic voltage and frequency scaling (DVFS) a reality. The CDLDO achieves this through a digital approach to voltage regulation, using a multiplexer to control power gates and a second controller to generate a second output for handling overshoot and droop events.

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Dynamic power control for integrated circuits that estimates power consumption based on block activities, enabling fast reaction to prevent overheating. The method identifies hardware units, determines block activities, estimates total power, and applies dynamic power controls to prevent chip overheating.

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A power management system for devices that dynamically allocates power credits to processing units based on predicted performance characteristics, enabling efficient peak power control without overdesigning the power management system. The system identifies device conditions, applies models to determine performance characteristics, and distributes power credits to manage peak power consumption for each processing unit. Power credits can be reallocated between units based on quality of service requirements, and units can degrade performance to accommodate power constraints.

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With the continuous improvement of on-chip integrated voltage regulators (IVRs) and fast, adaptive frequency control, dynamic voltage-frequency scaling (DVFS) transition times have shrunk from the microsecond to the nanosecond regime, providing immense opportunity to improve energy efficiency. The key to unlocking the continued improvement in V/f circuit technology is the creation of new, smarter DVFS mechanisms that better adapt to rapid fluctuations in workload demand.

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A voltage scaling system for reducing power consumption in processors. The system includes an oscillator, power management unit, frequency meter, table unit, and control unit. The oscillator generates a clock signal based on a code and power signal. The power management unit generates the power signal based on a requested voltage. The frequency meter measures the clock signal frequency and generates a control signal. The control unit generates the code and power signal control based on the frequency control signal, minimum code, and target frequency.

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A system-on-chip (SoC) for dynamic voltage and frequency scaling (DVFS) that optimizes power consumption by dynamically adjusting operating frequencies based on workload requirements. The SoC includes a processor with a DVFS module and a clock management unit (CMU), which work together to determine the optimal frequency for each core based on performance requirements and energy consumption calculations. The SoC also includes a memory that stores a DVFS program that executes the frequency scaling process.

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Dynamic voltage and frequency scaling (DVFS) is a widely used method to improve the energy efficiency of the CPU. Reducing the voltage and frequency during memory-intensive workloads can minimize power consumption without affecting performance, thereby improving overall energy efficiency. A finer-grained DVFS strategy leads to better energy efficiency. However, due to the limitation of voltage regulators, the implementation granularity of the current DVFS strategies is 100 s or more. This paper proposes that managing the CPUs power through a more fine-grained load-aware approach can improve CPU energy efficiency, even with limitations of the voltage regulators. This paper adds a more fine-grained dynamic frequency divider to the DVFS system. This mechanism can improve the processors energy efficiency in scenarios where DVFS does not take effect. This paper also proposes a DVFS management strategy based on finer-grained sampling. In order to improve the accuracy of performance estimation, we enhanced the state-of-the-art CRIT method to complete accurate memory time estimation in a ... Read More

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A power management system for multi-core processors that dynamically adjusts power consumption based on real-time event monitoring and weighted accumulation. The system uses distributed event counters to track power usage across multiple processing units, and a hierarchical accumulation mechanism to determine excess power consumption. This information is used to dynamically adjust power consumption of individual processing units, engines, and cache memory to optimize overall system power efficiency.

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A computing device that dynamically adjusts the CPU's power limit based on available power capacity, allowing the CPU to draw additional power when other components are idle, while preventing power spikes that can cause emergency throttling and capacitor "singing".

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Method and device for dynamically adjusting processor power consumption based on real-time power demand, enabling flexible and accurate frequency and voltage regulation. The system continuously monitors power consumption and temperature, and adjusts frequency and voltage based on a reference power consumption table that is dynamically updated based on current power demand. This approach enables real-time optimization of power consumption while maintaining processor performance and reliability.

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An electronic device with multiple cores that dynamically adjusts clock frequencies based on event types to optimize performance and power consumption. The device includes a system core that controls a clock generator to produce clock signals with frequencies determined by the type of event being processed, and applies these signals to the respective cores to perform the event.

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A power efficiency optimization system for processing units that dynamically adjusts voltage supply based on chip process variation. The system includes an adaptive voltage scaling module that determines an optimal voltage identification (VID) based on chip process variation, and outputs it to a voltage regulator. The voltage regulator adjusts the DC load line setting based on the optimal VID and regulates the voltage supplied to the processing unit. This enables power savings for nominal and best-case chips by eliminating the guard band required for worst-case corner chips.

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An electronic device determines an operating frequency of a processor based on a probability density function (PDF) that models the processor's utilization patterns. The device collects utilization variations over a time period, acquires a temporal PDF, and maps it to a corresponding PDF from a stored table. The device then uses the mapped PDF to determine the operating frequency for the next time period, taking into account the processor's unpredictability.

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Integrated circuit and computing system performing dynamic voltage and frequency scaling (DVFS) with adaptive voltage and frequency selection based on workload and environmental factors, enabling optimized performance and power consumption in mobile devices.

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A power management system for multi-core processors that dynamically adjusts voltage, frequency, and high-energy event (HEE) throttling based on individual core loads. The system uses counters to track HEEs and determines optimal configuration parameters for each core, taking into account operating system requests and conflicting requirements. By storing only practical configurations and using a hierarchical throttling approach, the system efficiently manages power consumption while maintaining performance.

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A power management system for integrated circuits that dynamically throttles individual IP circuits based on their local current consumption while preventing global power violations. The system includes a power controller that monitors current consumption across multiple IP circuits and generates a global violation signal when the total current exceeds a global budget. Local control circuits within each IP circuit can then throttle their own operation in response to both local and global signals, preventing unnecessary throttling of non-violating IP circuits.

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Integrated circuit for dynamic voltage and frequency scaling (DVFS) that considers power consumption of sub-blocks. The circuit includes active counters to track sub-block activity and a DVFS controller that calculates power consumption based on sub-block activity and total system activity. The controller adjusts operating conditions, such as frequency and voltage, based on the calculated power consumption.

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A power consumption control device for processors that dynamically adjusts power consumption based on real-time workload rather than fixed thresholds. The device calculates power consumption by monitoring key signals correlated with power usage, enabling precise control without compromising processor functionality. It can regulate both frequency and voltage in real-time to maintain optimal power levels, and employs multi-level current change rate thresholds to detect and respond to rapid power increases.

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A processor core that proactively mitigates voltage droop by predicting and preventing power surges through pipeline stage analysis. The core detects specific events in early pipeline stages that indicate impending power increases in later stages, and applies voltage mitigation countermeasures before the power surge occurs. This proactive approach enables voltage droop reduction and minimization, resulting in improved processor stability and performance.

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A method for directly and accurately monitoring and throttling power consumption of a chip, particularly in high-performance applications like machine learning ASICs, to match a desired power profile. The method involves using a dedicated power monitoring circuit to measure actual power consumption, rather than inferring it from activity metrics, and dynamically adjusting power supply based on real-time measurements to prevent power surges and thermal issues.

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Dynamic frequency scaling is broadly available among different modern computer architectures, making it possible to improve the performance and energy efficiency of an application by carefully setting the core frequency. However, while an exhaustive tuning is feasible on simple single-kernel applications, in real-world applications comprised of multiple tasks, the set of possible frequency setting combinations is too large to be exhaustively evaluated.

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An integrated circuit (IC) power management system that enables localized power control within a power block. The system includes individually programmable head switch cells that can be dynamically turned on and off to selectively power down specific regions of the power block, thereby reducing power consumption and mitigating hold timing issues.

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A system for coherently managing multiple power management circuits operating in different time domains, including high-speed and low-speed mechanisms, to optimize power consumption and performance in electronic systems. The system includes control circuitry that coordinates operation of the mechanisms, enabling coordinated power management across different domains and preventing mechanisms from working at cross-purposes.

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Preventing battery under-voltage shutdown of information handling systems by dynamically adjusting the maximum instantaneous power envelope of a processor as the capacity of a battery power source decreases.

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Power management system for integrated circuits that dynamically adjusts power consumption based on actual execution characteristics. The system uses a power estimator to predict operation power consumption and withdraw corresponding credits, while a power sensing circuit monitors supply node characteristics to generate a power value. If actual power consumption is less than predicted, the power sensing circuit refunds a portion of the withdrawn credits, enabling more efficient power management.

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A digital voltage controller for adaptive voltage regulation in power management systems. The controller uses a digital LDO regulator with a novel timing circuit that enables fast response times while maintaining low dropout voltage. The timing circuit employs a delay line and flip-flops to generate a timing margin signal that is compared to a reference signal to control the number of switches turned on between the supply rail and the circuit. This approach enables precise voltage regulation with minimal voltage droop, making it suitable for high-performance applications.

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A digital low dropout (LDO) voltage regulator that decouples steady-state response from transient performance using asynchronous, non-linear control. The regulator employs a clockless comparator to detect output voltage drops and asynchronously activates all power transistors to mitigate voltage droop, achieving fast recovery under large load transients. The design enables per-core dynamic voltage and frequency scaling (DVFS) with a regulated voltage range of 0.15V to 1.15V and a load current range of up to 125mA.

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A method for power management in a multi-core device that dynamically adjusts the operating voltage of a shared power rail based on the operating states of individual cores. Each core reports its operating state to an aggregator, which selects a voltage level for the shared rail that is optimal for the active cores, rather than using the maximum voltage across all cores. This approach reduces power consumption compared to traditional methods that operate at maximum voltage.

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Dynamic voltage and frequency scaling (DVFS) has been the subject of extensive study for the past two decades. DVFS has been shown to dramatically reduce power consumption and thermal stress and is now routinely used in both embedded and general-purpose systems. However, DVFS research has largely focused on independently controlling voltage and frequency for individual cores. Less well studied is the case of global DVFS (GDVS), where multiple cores share the same voltage and clock. A very simple GDVS heuristic is presented in this letter; it is lightweight and effectively exploits task profiling information to appropriately sequence task executions. Simulation studies show its effectiveness.

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Dynamic voltage frequency scaling (DVFS) has been widely adopted for run-time power management of various processing units. In the case of neural processing units (NPUs), power management of neural network applications is required to adjust the frequency and voltage every layer to consider the power behavior and performance of each layer. Unfortunately, DVFS is inappropriate for layer-wise run-time power management of NPUs due to the long latency of voltage scaling compared with each layer execution time. Because the frequency scaling is fast enough to keep up with each layer, we propose a layer-wise dynamic frequency scaling (DFS) technique for an NPU. Our proposed DFS exploits the highest frequency under the power limit of an NPU for each layer. To determine the highest allowable frequency, we build a power model to predict the power consumption of an NPU based on a real measurement on the fabricated NPU. Our evaluation results show that our proposed DFS improves frame per second (FPS) by 33% and saves energy by 14% on average, compared with DVFS.

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Dynamic voltage and frequency scaling (DVFS) is a widely used solution to reduce power consumption. Modern multi-core architectures support core-level DVFS, where each core has its own power supply and can change its frequency independently from other cores. This paper aims at optimizing power consumption of multi-core processors while ensuring deadline constraints of real-time periodic tasks. From theoretical aspects, we prove a tight lower bound of power consumption for executing real-time tasks, which indicates to what extent scheduling algorithms can approach. From practical aspects, we propose a Power Scaling Algorithm (PSA) to assign real-time periodic tasks to a power efficient platform. PSA not only determines the optimal frequencies for each core, but also provides the appropriate number of active cores, which can skip the local optimum and achieve the global minimum. This lower power bound is validated by several extensive experiments.

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Voltage regulators usually serve the purpose of generating a constant regulated output voltage. By means of control loops, a stable and precise supply is generated from an unregulated input voltage. What purpose, then, does dynamic voltage scaling (DVS) serve?

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A power management system for computing systems that dynamically throttles processor performance to prevent power excursions while maintaining optimal system operation. The system includes a power controller that monitors system power consumption and asserts a critical signal to processor throttling engines when power thresholds are exceeded. The throttling engines then execute a sequence of throttling states to reduce power consumption while maintaining system performance.

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A data processing system includes a data processor and a voltage regulator. The data processor operates in response to a power supply voltage, and includes at least one power supply voltage terminal for receiving the power supply voltage and through which a power supply current is conducted, a data processing circuit coupled to the at least one power supply voltage terminal and operating using the power supply voltage, a register for storing a nominal value of the power supply voltage, an electrical design current (EDC) limit, and an EDC slope, wherein the EDC slope specifies a desired voltage-current relationship of the power supply voltage when the power supply current exceeds the EDC limit, and a port controller coupled to the register and to an output port. The voltage regulator is coupled to the output port of the data processor for providing the power supply voltage according to the nominal value of the power supply voltage, the EDC limit, and the EDC slope.

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