Dynamic Voltage and Frequency Scaling for Power Efficiency

Selectively throttling subsystems of a battery-powered computing device to prevent brownouts and improve user experience by avoiding excessive battery voltage droops. When ROP subsystem power usage is high, those devices are throttled before processor cores. Multiple layers of brown-out prevention are applied asynchronously to different domains and subsystems. The throttling is triggered when total power consumption exceeds thresholds, with ROP subsystems throttled first. This prevents aggressive throttling of the processor cores.

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A method for dynamically optimizing processor frequency and voltage to maximize performance while maintaining reliability. The method involves analyzing processor states and conditions to determine optimal frequency scaling indexes, which are then used to select a target clock frequency. The method also includes adaptive voltage control to mitigate voltage droops, with droop mitigation enabled when the core voltage falls below a threshold. The voltage control loop offsets load line uplift to maintain voltage below the reliability limit, while protecting against performance loss from excessive droop mitigation.

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A power management system for processing units that dynamically adjusts current draw in response to sudden workload changes, preventing performance degradation and maintaining functionality during rapid transitions between low and high processing demands.

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A Dynamic Voltage and Frequency Scaling (DVFS) controller that optimizes performance and power efficiency by dynamically adjusting operating voltage and frequency based on resonance frequency calculated from the entire power system's frequency response, including the power management unit, power delivery network, and processing subblocks. The controller receives feedback signals from the system and updates voltage and frequency control signals to maintain stable operation even in voltage drooping conditions.

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A method for adjusting CPU frequency in mobile devices that improves energy efficiency by dynamically adjusting the target CPU load based on the actual load and a threshold error. The method includes setting the CPU frequency for a current cycle based on the prior cycle's load and target load, detecting the current load, and adjusting the frequency based on the difference between the target and actual loads. The target load is dynamically adjusted based on the load error and a threshold error, enabling the CPU to operate at the optimal frequency for the current workload.

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A dynamic voltage and frequency scaling (DVFS) system for multi-core processors that dynamically allocates power to individual cores based on their performance and power consumption. The system receives power and performance metrics from each core, calculates a power margin based on a target power budget, and adjusts the power index of each core accordingly. The system also determines whether each core can increase its bus frequency or core frequency based on utilization and bandwidth metrics, and adjusts these frequencies accordingly.

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Dynamic voltage and frequency scaling (DVFS) technique for integrated circuits with multiple processing cores sharing a voltage rail. The technique uses a ruler-follower mechanism where a core can register as a ruler or follower, with the ruler core influencing the frequency of follower cores. The DVFS manager adjusts core frequencies and voltage rail based on mapping rules and constraints to optimize high voltage residency and minimize power consumption.

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Apparatus for dynamic voltage and frequency scaling (DVFS) of integrated components in a System on a Chip (SoC), comprising a plurality of components with assigned throttling priorities and a logic to selectively throttle components based on their priority order.

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Adaptive voltage scaling system for computing systems that optimizes power consumption by dynamically adjusting operating voltage in real-time based on workload demands, while maintaining stability and reliability through continuous monitoring of physical parameters and operating conditions. The system integrates dynamic voltage and frequency scaling (DVFS) with adaptive voltage and code scaling (DVCS) to achieve optimal energy efficiency and performance.

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A power management system for extension cards or circuit boards that actively regulates current consumption in real-time. The system includes a current sensing circuit that measures the current drawn by the extension card from the motherboard, and a controller that generates a control signal based on the measured current compared to a target current. The control signal is applied to the extension card to adjust its current consumption, enabling dynamic power management that can respond to changing system conditions.

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Power management in integrated circuits like system-on-chips (SoCs) to reduce power consumption. The power management unit (PMU) monitors power supply voltages, currents, and temperatures in the SoC and triggers power reduction if conditions exceed thresholds. The PMU has wired and serial trigger circuits to communicate with the SoC. Wired circuits provide fast responses for voltage and current conditions, while serial circuits provide slower responses for temperature. The PMU triggers power reduction to prevent erroneous operation if supply voltages drop, currents exceed limits, or temperatures rise.

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A system and method for power throttling in multicore systems that measures current draw on the main power rail to detect power surges and trigger throttling when thresholds are exceeded, including both absolute current levels and current slew rates.

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A voltage regulator (VR) control method that predicts large load current transients and proactively increases its response speed to minimize voltage undershoot/overshoot. The method uses predictive load transient information from the load device to generate a turbo signal that activates the VR's high-response mode before the transient occurs. The VR can also generate a power throttling signal to reduce load current transients when operating in high-response mode.

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Efficient power management for integrated circuits, particularly in multi-core processors, is achieved by dividing functional blocks into separate power domains, each with its own voltage regulator, allowing for independent power management and reduced power consumption.

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A semiconductor device that controls temperature through dynamic voltage frequency scaling (DVFS) by monitoring the operating clock's critical path and adjusting the supply voltage in response to frequency comparison results. The device includes a thermal management unit, clock management unit, power management unit, and DVFS block with a critical path monitor, frequency monitor, target frequency module, adder, and decide voltage module. The DVFS block compares the target frequency with the current frequency and generates deciding results to control the supply voltage, which is then provided to the clock generator.

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A method and apparatus for detecting voltage droop in a processor's supply voltage. The method involves receiving a clock signal at a tap sampled delay line powered by the same supply voltage, splitting the signal into two paths, sampling the signal at multiple taps, and measuring the change in clock edge position between samples to determine the magnitude of voltage droop. When voltage droop is detected, the method generates a lower-frequency clock signal to mitigate the droop. The apparatus includes a tap sampled delay line and clock signal modification circuitry to implement this method.

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A computational digital low dropout (CDLDO) regulator that computes a required solution for regulating an output supply as opposed to traditional feedback controllers. The CDLDO regulator autonomously tunes out the effects of process-voltage-temperature (PVT) and other non-idealities, enabling GHz-speed regulation and making fast dynamic voltage and frequency scaling (DVFS) a reality. The CDLDO achieves this through a digital approach to voltage regulation, using a multiplexer to control power gates and a second controller to generate a second output for handling overshoot and droop events.

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Dynamic power control for integrated circuits that estimates power consumption based on block activities, enabling fast reaction to prevent overheating. The method identifies hardware units, determines block activities, estimates total power, and applies dynamic power controls to prevent chip overheating.

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A power management system for devices that dynamically allocates power credits to processing units based on predicted performance characteristics, enabling efficient peak power control without overdesigning the power management system. The system identifies device conditions, applies models to determine performance characteristics, and distributes power credits to manage peak power consumption for each processing unit. Power credits can be reallocated between units based on quality of service requirements, and units can degrade performance to accommodate power constraints.

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With the continuous improvement of on-chip integrated voltage regulators (IVRs) and fast, adaptive frequency control, dynamic voltage-frequency scaling (DVFS) transition times have shrunk from the microsecond to the nanosecond regime, providing immense opportunity to improve energy efficiency. The key to unlocking the continued improvement in V/f circuit technology is the creation of new, smarter DVFS mechanisms that better adapt to rapid fluctuations in workload demand.

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