Driver Circuits for Micro-LED Displays

Micro-LED display device with improved electrode design for better electrical connection and reliability. The display has pixels with multiple transistors, electrodes, and micro-LEDs. The micro-LEDs have a first electrode connected to the pixel electrode and a second electrode exposed. A common electrode connects to the second electrodes of all micro-LEDs and contact electrodes of the pixels. This allows direct electrical connection of the common electrode to the micro-LED electrodes without interposing wiring. Metal wiring connects the contact electrodes. The common electrode and wiring are between insulating layers above the transistors.

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Compact, high-performance optoelectronic component for integrating LEDs and control electronics in a single package. The component has an optoelectronic chip mounted in a recess with a tilted side wall. The chip's electrical contacts connect to pads on a control chip using conductive paths applied to the side wall. This allows the LED and control electronics to be stacked in a compact housing without needing separate leads. The tilted wall guides the conductors directly over the chips without adding height. The housing can also have cutouts with tilted sides for connecting the LED chip's pads to an external leadframe.

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Electronic device and display panel design to reduce vertical bright lines and shaking in displays. It achieves this by arranging the subpixels and connecting the electrodes in a specific way. The subpixels have electrodes connected to a single signal line. The first and second electrodes of adjacent subpixels are on one side of the line, while the third and fourth electrodes are on the other side. This alternating layout helps distribute brightness evenly when scanning the lines.

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A backplane design for microLED displays with improved yield by protecting the connecting terminals from oxidation and corrosion. The backplane has the connecting terminals located inside via holes on the flexible substrate instead of exposed on the surface. This prevents environmental degradation and improves reliability. The terminals have portions between the substrate and passivation layer, and inside the via. This allows electrical connection through the via hole to the substrate signal traces. It enables using any material for the terminals, not just ones that can withstand wet etching. The protected terminals improve yield compared to exposed terminals prone to oxidation and corrosion.

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An allGaNbased monolithic activematrix microLED system that integrates metalinsulatorsemiconductor highelectronmobility transistors (MIS HEMTs) with lightemitting diodes (LEDs) is demonstrated. The proposed structure employs direct electron injection from the 2D gas (2DEG) in a HEMT, serving as ntype layer, into quantum wells of LEDs. A 2HEMT1LED pixel configuration fabricated one epitaxial growth, enabling precise control LED light output through combination select and drive HEMTs. achieved maximum optical density 0.5 Wcm 2 . 2 matrix constructed row column lines connected via HEMTs, demonstrating capability for individual control.

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Display device with optimized voltage distribution for subpixels containing differently colored LEDs. The subpixels each have multiple groups of LEDs connected in series. The number of series connections is different in the blue/green subpixel versus the red subpixel. This reduces voltage loss in the red subpixel compared to equal series connections in all subpixels. It allows similar operating voltages for all subpixels, simplifying circuitry.

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Display panel design to improve display uniformity by reducing via hole defects around the perimeter of the display region. The panel has a base substrate with a main display area. Inside the display area are pixel groups with light-emitting units. The signal lines to the pixel groups have a mix of metal and transparent lines. Metal lines are used for signals that have a greater impact on display brightness. This reduces the resistance difference between the signal lines inside and outside the display area. This reduces via hole defects around the display perimeter, improving display uniformity.

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Compensation circuit for display devices to improve stability and reduce abnormal images when switching between voltage compensation methods. The circuit has a delay component that allows gradual transition between methods instead of instant switching. When display compensation uses common voltage, the delay outputs common voltage to the display and operating voltage to the amplifier. When using polarity inversion, the delay outputs operating voltage to the amplifier and common voltage to the display. This prevents common voltage loss during switching.

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Reducing color deviation in a display device when driven at variable frequencies to prevent tearing. The technique involves changing the voltage levels of the data signals in the overlap period when a dummy scan operation and a second active scan operation are happening simultaneously. This reduces color differences between upper and lower areas of the display due to variable frame rates.

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Pixel circuit for display panels to improve low brightness and grayscale performance and reduce unevenness. The circuit has a driving module to drive the display element and a shunt branch connected between the element electrode and a reference voltage line. This allows part of the driving current to be shunted to the reference line. This increases the effective brightness of the element through current amplification. This helps compensate for characteristic fluctuations in low brightness/grayscale that affect display quality. By selectively turning on the shunt branch at low brightness, it improves low brightness/grayscale uniformity.

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Integrating micro LEDs with digital and analog circuitry in a stacked configuration to enable compact, power-efficient display systems. The technique involves reconstituting a semiconductor wafer with a layer containing the micro LEDs after forming the driver circuitry on a separate wafer. This allows integrating the micro LED arrays with the digital and analog circuits in a common wafer. The process involves singulating and bonding micro LED wafers to a driver wafer, then removing the substrate and forming vertical connections through the stack. It eliminates the need for wafer size mismatch and waste compared to bonding larger wafers.

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Reducing power consumption in display devices by selectively supplying clock signals to scan circuits in each horizontal line. A clock controller generates control signals in response to scan signals. A clock selector supplies clock signals to the scan circuits in each horizontal line only when the control signals are asserted. This avoids unnecessary clocking during blank periods.

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Driving circuit for displays with improved stability and reliability. The circuit has a pull-up node control circuit, a pull-down node control circuit, and an output circuit. The output circuit drives the display pixels. The channel length of some transistors in the output circuit, pull-up node control, and reset terminal control circuits is increased compared to other transistors in the circuit. This improves stability of those transistors when driving large currents. The increased channel length is compensated by wider active areas. The increased channel length and wider active areas improve stability and reliability of the circuit, especially for large current driving.

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Reducing latency in display processing when updating multiple regions of interest (ROIs) of a frame to prevent tearing artifacts. The technique involves using both software and hardware triggers for ROI updates instead of relying solely on software triggers. When a software trigger indicates to start an ROI update, hardware triggers are generated based on completion of the ROI. This allows faster chaining of ROI updates compared to waiting for software triggers. Hardware triggers can be faster due to direct memory access and internal pipelining.

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Display substrate with improved stability of the drive transistor in high resolution, high frequency displays. The substrate has a shield electrode in the second conductive layer, parallel to the base substrate, that shields the first connection electrode from voltage jumps on the scan signal line. This prevents voltage spikes from the scan line affecting the gate of the drive transistor, improving stability and display quality. The shield electrode is connected to the power supply line. The shield overlaps the scan line and connection electrode projections on the substrate.

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A display device and method to mitigate luminance variations when using different refresh rates. The display has scan lines and initialization lines. During frames, scan signals are sent to the scan lines and initialization signals to the initialization lines. If initialization signals overlap during active and blank periods, scan signals with different widths are sent to scan lines based on the area of the display. This prevents luminance differences when displaying images at varied refresh rates.

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Chip on film technology with high pin count capability for high resolution displays. The chip on film has a unique layout to enable very high pin counts while maintaining yield and processability. The chip design has separate first and second leadframes, with the first leadframes between the pad layer and substrate. This allows denser pad arrays and smaller lead pitch. The second leadframes have raised structures on the substrate that align with the second leadframe connections. This allows high pin count without expanding the chip size. The layout enables very high pin counts while maintaining yield and processability compared to conventional chip on films.

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Driver module for display devices to reduce signal delay and voltage differences at far gate line terminals in GOA bilateral cross drive configurations. The driver module has separate control and driver circuits for each level of gate lines. Each level driver circuit provides the clock signal to its gate line. The control circuits simultaneously drop the far terminal voltage when the near terminal voltage drops, synchronizing the signal delays. This prevents overcharging, voltage differences, and display issues. The separate control circuits also help reduce leakage compared to single-sided GOA.

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Reducing the load on data lines in a display apparatus to improve performance and reduce non-display area by incorporating capacitors in the design. The capacitors are formed by connecting branch lines to main data lines and also using separate bridge lines. This allows forming capacitors between the branch lines and main lines as well as between bridge lines. This reduces the load on the data lines when transmitting signals to the pixel circuits, improving performance. By using these internal capacitors, the need for external capacitors is reduced, which can save space and prevent expansion of the non-display area around the display.

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Pixel circuit design for displays that enables reliable threshold voltage compensation for improved display quality at high frame rates. The circuit separates data writing and voltage compensation stages. A reset circuit controls connections to initialize voltages. An adjustment circuit modulates node voltages. A light emission control circuit sets gate voltage. The drive circuit transmits signals. This allows flexible compensation signals for reliable threshold adjustment without timing constraints.

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